Intel announce new package
The vital step in scaling to 20GHz
Intel has today announced a new packaging technology that will help the company build processors with more than a one billion transistor count at about 20GHz in the next few years. The technology is called "Bumpless Build-Up Layer" or BBUL packaging. Today, modern silicon chips are connected electrically and mechanically to their packaging via tiny balls of solder called "bumps". As the speed of processors increases, bumps and other factors including the thickness of the packaging and the number of connection points could become a performance limiter. With processor speed doubling every 18 months or so, it won't be long before a new technology is called for. This is where BBUL comes in, deliberately circumventing all three potential pitfalls. Eliminating the use of bumps completely, and ignoring the practice of attaching the silicon die to the package, BBUL grows the package around the silicon. High-speed copper connections (similar to those used in competitor AMD's current processor lines) are used to connect the die to the different layers of the package. This reduces the physical thickness of the processor package and reduces power consumption as a by-product. Intel's new packaging also gives them the chance to build multi-chip solutions in one package. It also opens the doors to high-performance embedded processors, a market Intel will be delighted to make inroads into. Expect to hear about networking equipment and similar devices utilizing BBUL… …but don't expect to hear much about it in the immediate future. Intel is targeting the implementation of BBUL as a packaging option between 2006 and 2007. Naturally, we'll have our offspring bring you in-depth commentary on the technology nearer the time!
